1. Field of the Invention
The present invention relates to an array substrate for an in-plane switching (IPS) mode liquid crystal display (LCD) device and more particularly to an array substrate for an IPS mode LCD device having an improved aperture ratio.
2. Discussion of the Related Art
A related art liquid crystal display (LCD) device uses optical anisotropy and polarization properties of liquid crystal molecules. The liquid crystal molecules have a definite alignment direction as a result of their thin and long shapes. The alignment direction of the liquid crystal molecules can be controlled by applying an electric field across the liquid crystal molecules. In other words, as the intensity or direction of the electric field is changed, the alignment of the liquid crystal molecules also changes. Since incident light is refracted based on the orientation of the liquid crystal molecules due to the optical anisotropy of the liquid crystal molecules, images can be displayed by controlling light transmissivity.
Since the LCD device including a thin film transistor (TFT) as a switching element, referred to as an active matrix LCD (AM-LCD) device, has excellent characteristics of high resolution and displaying moving images, the AM-LCD device has been widely used.
The AM-LCD device includes an array substrate, a color filter substrate and a liquid crystal layer interposed therebetween. The array substrate may include a pixel electrode and the TFT, and the color filter substrate may include a color filter layer and a common electrode. The AM-LCD device is driven by an electric field between the pixel electrode and the common electrode to have excellent properties of transmittance and aperture ratio. However, since the AM-LCD device uses a vertical electric field, the AM-LCD device has a bad viewing angle.
An in-plane switching (IPS) mode LCD device may be used to resolve the above-mentioned limitations. FIG. 1 is a cross-sectional view of the related art IPS mode LCD device. As shown in FIG. 1, the related art IPS mode LCD device includes the array substrate and the color filter substrate separated apart from and facing each other. The array substrate includes a first substrate 10, a common electrode 17 and a pixel electrode 30. Though not shown, the array substrate may include a TFT, a gate line, a data line, and so on. The color filter substrate includes a second substrate 9, a color filter layer (not shown), and so on. A liquid crystal layer 11 is interposed between the first substrate 10 and the second substrate 9. Since the common electrode 17 and the pixel electrode 30 are formed on the first substrate 10 on the same level, a horizontal electric field “L” is generated between the common and pixel electrodes 17 and 30.
FIGS. 2A and 2B are cross-sectional views showing turned on/off conditions of the related art IPS mode LCD device. As shown in FIG. 2A, when the voltage is applied to the IPS mode LCD device, liquid crystal molecules 11a above the common electrode 17 and the pixel electrode 30 are unchanged. But, liquid crystal molecules 11b between the common electrode 17 and the pixel electrode 30 are horizontally arranged due to the horizontal electric field “L”. Since the liquid crystal molecules 11 are arranged by the horizontal electric field “L”, the IPS mode LCD device has a characteristic of a wide viewing angle. For example, the IPS mode LCD device has a viewing angle of about 80 degrees to about 85 degrees without an image inversion or a color inversion.
FIG. 2B shows a condition when the voltage is not applied to the IPS mode LCD device. Because an electric field is not generated between the common and pixel electrodes 17 and 30, the arrangement of liquid crystal molecules 11 is not changed.
FIG. 3 is a plane view of a portion of an array substrate for the related art IPS mode LCD device. In FIG. 3, the array substrate 40 includes a gate line 43, a common line 47, a data line 60, a plurality of common electrodes 49a and 49b, a plurality of pixel electrodes 70 and a thin film transistor (TFT) Tr. The gate line 43 extends along a first direction, and the common line 47 is parallel to the gate line 43. The data line 60 extends along a second direction being different from the first direction to cross the gate line 43 and the common line 47. Particularly, a crossing of the gate and data lines 43 and 60 defines a pixel region P.
The TFT Tr is disposed at a crossing portion of the gate and data lines 43 and 60. The TFT Tr includes a gate electrode 45, a semiconductor layer 50, a source electrode 53 and a drain electrode 55. The source electrode 53 extends from the data line 60, and the gate electrode 45 extends from the gate line 43. The pixel electrodes 70 is connected to the drain electrode 55 through a drain contact hole 67 and disposed in the pixel region P. The common electrodes 49a and 49b are alternately arranged with the pixel electrodes 70 and extend from the common line 47.
The common electrodes include first common electrodes 49a and a second common electrode 49b. The second common electrode 49b is disposed between the first common electrodes 49a, and each of the first common electrodes 49a is disposed to be adjacent to the data line 60. In this case, the first common electrodes 49a is spaced apart from the data line 60 with a pre-determined distance. A common voltage is applied into the common electrodes 49a and 49b through the common line 47, which is across the pixel region P, and an additional compensation or tuning for a difference in a common voltage resulted from charging of a constant voltage is required. Accordingly, production costs increase and a fabricating process is complicated.
In addition, since the first common electrodes 49a is spaced apart from the data line 60 to prevent signal interference between the first common electrodes 49a and the data line 60, an aperture ratio of the IPS mode LCD device decreases.